Given a memory and an I/O device on a bus as shown below:
64 bit wide bus, synchronous, 50MHz clock
==============================================================
| |
address and | two 32-bit data address and | two 32-bit data
word count | words sent word count | words received
received in | in one clock sent in one | in one clock
one clock | clock |
| |
+—–+—–+—–+—–+ +—–+—–+
| | | | |Registers | I/O device|
+—–+—–+—–+—–+ | receiving |
| RAM memory that is | | word-count|
| four 32-bit words wide| | words of |
| and has output | | data |
| registers for four | +———–+
| words |
+———————–+
The system operates by the I/O device sending an address and
word count to the memory. The memory uses the address to start
a memory access that brings four 32-bit words into the memory
output registers. In parallel, [the memory starts the access of
the next fou
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