IES-2006 VLSI Design Principles

IES-2006 VLSI Design Principles

Description
This exam is being set as an assignment. You may use all resources that have been made available to
you.
You will need to complete all questions in the paper.
Total number of marks: 80.
Issue date: Monday 6th April 2020, 09:00.
Due date: Friday 24th April 2020, 23:59.
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Easter 1st Sit Attempt 1
2
IES2006: VLSI Design Principles
Answer all questions. Total 80 marks
1. Types of ASIC
Compare the construction of Standard Cell Application Specific Integrated Circuits (Standard Cell
ASICs or Cell-based ICs: CBICs) with Field Programmable Gate Arrays (FPGAs). Be sure
to describe their basic features and include a discussion of the degree of customisation of
the different mask levels in the chip’s construction, i.e. explain which of the mask levels
are unique to a given design and which are common to all designs using that particular type
of ASIC. Draw diagrams to illustrate the differences between the two types of chip.[10]
2. Principles of programmable ASIC technology
The following expression (due to Elmore) gives an estimate of the delay between nodes v0 and vi in
an RC tree with n nodes:
Find the Elmore approximation of the delay between nodes v0 and v3 in the following RC tree. All
values are in farads (note that 1 fF = 10-15F) and ohms:
[10]
å=
=
n
k
Di RkiCk
1
t
3
3. Principles of ASIC Design
a) Describe the process of event-based simulation, as applied to the simulation of VHDL code
for FPGA design. Include a discussion of delta time in your description. [5]
b) Code snippet 1 gives an extract from a two-process description of a Finite State Machine
in VHDL. Briefly describe what each of the two processes accomplishes. Explain at what
time in the simulation cycle assignments are made to signals when simulating a VHDL
process. What is the relevance of that timing when considering the line of code that is
underlined in Code snippet 1? [5]
FSM_FF: process (CLK, RESET) begin
if RESET=’1′ then
STATE <= START ;
elsif CLK’event and CLK=’1′ then
STATE <= NEXT_STATE ;
end if;
end process FSM_FF ;
FSM_LOGIC: process (STATE , X)
begin
NEXT_STATE <= STATE ;

end if ;

end case ;
end process FSM_LOGIC ;
Code snippet 1
4
4. Principles of ASIC Design – Extension question
A signal processing unit in a communications system requires the calculation of the sum of sixteen
binary numbers, each of 8 bits. The designer has decided to implement the required adding machine
as a four-level adder tree. The first level of the adder tree sums eight pairs of 8-bit numbers using
eight instances of a pre-designed fast-adder block. The critical delay in the adder block is 25ns. The
adder block has been designed with 12-bit operands, so there will be no problem with overflow
when pairs of results are added. The second level sums the eight results from the previous stage with
four more adders. The third stage will have two adders, and the fourth stage one adder.
a) Draw a diagram of the adder tree, labelling each bus with its width. [5]
b) Assuming the inputs and the final sum output are stored in registers with setup and hold
times of 2ns, what will be the maximum clock frequency for the system? What is the throughput at

i) one row and
ii) three rows of pipeline registers.
For each case find the maximum clock frequency, the pipeline latency and the maximum
throughput (in calculations per second). Be sure to include the effect of setup time and hold time
on your calculations. [30]

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